3D-transistor array based on horizontally suspended silicon nano-bridges grown via a bottom-up technique

3D-transistor array based on horizontally suspended silicon nano-bridges grown via a bottom-up technique

© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Bibliographische Detailangaben
Veröffentlicht in:Advanced materials (Deerfield Beach, Fla.). - 1998. - 26(2014), 12 vom: 26. März, Seite 1929-34
1. Verfasser: Oh, Jin Yong (VerfasserIn)
Weitere Verfasser: Park, Jong-Tae, Jang, Hyun-June, Cho, Won-Ju, Islam, M Saif
Format: Online-Aufsatz
Sprache:English
Veröffentlicht: 2014
Zugriff auf das übergeordnete Werk:Advanced materials (Deerfield Beach, Fla.)
Schlagworte:Journal Article Research Support, Non-U.S. Gov't VLS bottom-up bridge field effect transistor memory nanowire silicon surround gate
Beschreibung
Zusammenfassung:© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Integrated surround-gate field-effect-transistors enabled by bottom-up synthesis of nano-bridges are demonstrated. Horizontally oriented silicon nano-bridge devices are fabricated avoiding the rigorous processes for aligning and contacting nanowires grown via a bottom-up technique. Evaluation of electrical properties and a memory device application of the transistors are presented
Beschreibung:Date Completed 25.11.2014
Date Revised 30.09.2020
published: Print-Electronic
Citation Status PubMed-not-MEDLINE
ISSN:1521-4095
DOI:10.1002/adma.201304245