Vapor Deposition of Bilayer 3R MoS2 with Room-Temperature Ferroelectricity

Vapor Deposition of Bilayer 3R MoS2 with Room-Temperature Ferroelectricity

© 2024 Wiley‐VCH GmbH.

Bibliographische Detailangaben
Veröffentlicht in:Advanced materials (Deerfield Beach, Fla.). - 1998. - 36(2024), 32 vom: 03. Aug., Seite e2400670
1. Verfasser: Jiang, Hanjun (VerfasserIn)
Weitere Verfasser: Li, Lei, Wu, Yao, Duan, Ruihuan, Yi, Kongyang, Wu, Lishu, Zhu, Chao, Luo, Lei, Xu, Manzhang, Zheng, Lu, Gan, Xuetao, Zhao, Wu, Wang, Xuewen, Liu, Zheng
Format: Online-Aufsatz
Sprache:English
Veröffentlicht: 2024
Zugriff auf das übergeordnete Werk:Advanced materials (Deerfield Beach, Fla.)
Schlagworte:Journal Article bilayer 3R MoS2 chemical vapor deposition piezoelectric force microscopy scanning Kelvin Probe microscopy sliding ferroelectricity
Beschreibung
Zusammenfassung:© 2024 Wiley‐VCH GmbH.
Two-dimensional ultrathin ferroelectrics have attracted much interest due to their potential application in high-density integration of non-volatile memory devices. Recently, 2D van der Waals ferroelectric based on interlayer translation has been reported in twisted bilayer h-BN and transition metal dichalcogenides (TMDs). However, sliding ferroelectricity is not well studied in non-twisted homo-bilayer TMD grown directly by chemical vapor deposition (CVD). In this paper, for the first time, experimental observation of a room-temperature out-of-plane ferroelectric switch in semiconducting bilayer 3R MoS2 synthesized by reverse-flow CVD is reported. Piezoelectric force microscopy (PFM) hysteretic loops and first principle calculations demonstrate that the ferroelectric nature and polarization switching processes are based on interlayer sliding. The vertical Au/3R MoS2/Pt device exhibits a switchable diode effect. Polarization modulated Schottky barrier height and polarization coupling of interfacial deep states trapping/detrapping may serve in coordination to determine switchable diode effect. The room-temperature ferroelectricity of CVD-grown MoS2 will proceed with the potential wafer-scale integration of 2D TMDs in the logic circuit
Beschreibung:Date Revised 08.08.2024
published: Print-Electronic
Citation Status PubMed-not-MEDLINE
ISSN:1521-4095
DOI:10.1002/adma.202400670