Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing

Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing

© 2024 The Authors. Advanced Materials published by Wiley‐VCH GmbH.

Bibliographische Detailangaben
Veröffentlicht in:Advanced materials (Deerfield Beach, Fla.). - 1998. - 36(2024), 24 vom: 08. Juni, Seite e2310015
1. Verfasser: Lee, Taeran (VerfasserIn)
Weitere Verfasser: Jung, Kil-Su, Seo, Seunghwan, Lee, Junseo, Park, Jihye, Kang, Sumin, Park, Jeongwon, Kang, Juncheol, Ahn, Hogeun, Kim, Suhyun, Lee, Hae Won, Lee, Doyoon, Kim, Ki Seok, Kim, Hyunseok, Heo, Keun, Kim, Sunmean, Bae, Sang-Hoon, Kang, Seokhyeong, Kang, Kibum, Kim, Jeehwan, Park, Jin-Hong
Format: Online-Aufsatz
Sprache:English
Veröffentlicht: 2024
Zugriff auf das übergeordnete Werk:Advanced materials (Deerfield Beach, Fla.)
Schlagworte:Journal Article 2D vdW layered materials brain‐inspired parallel computing multivalued logic computing negative‐differential‐resistance device
Beschreibung
Zusammenfassung:© 2024 The Authors. Advanced Materials published by Wiley‐VCH GmbH.
Negative-differential-resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal-insulator-semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static-random-access-memory, which are essential components in the development of multivalued logic computing technology
Beschreibung:Date Revised 13.06.2024
published: Print-Electronic
Citation Status PubMed-not-MEDLINE
ISSN:1521-4095
DOI:10.1002/adma.202310015