Review of Semiconductor Flash Memory Devices for Material and Process Issues

© 2022 Wiley-VCH GmbH.

Bibliographische Detailangaben
Veröffentlicht in:Advanced materials (Deerfield Beach, Fla.). - 1998. - 35(2023), 43 vom: 19. Okt., Seite e2200659
1. Verfasser: Kim, Seung Soo (VerfasserIn)
Weitere Verfasser: Yong, Soo Kyeom, Kim, Whayoung, Kang, Sukin, Park, Hyeon Woo, Yoon, Kyung Jean, Sheen, Dong Sun, Lee, Seho, Hwang, Cheol Seong
Format: Online-Aufsatz
Sprache:English
Veröffentlicht: 2023
Zugriff auf das übergeordnete Werk:Advanced materials (Deerfield Beach, Fla.)
Schlagworte:Journal Article Review NAND architecture charge-trapping memory layer stacking material and process issues multilevel data
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520 |a Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176-layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400-500) due to the total allowable chip thickness, which will be reached within 6-7 years. This review summarizes the current status and critical challenges of charge-trap-based flash memory devices, with a focus on the material (floating-gate vs charge-trap-layer), array-level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell-level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices 
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650 4 |a Review 
650 4 |a NAND architecture 
650 4 |a charge-trapping memory 
650 4 |a layer stacking 
650 4 |a material and process issues 
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700 1 |a Yong, Soo Kyeom  |e verfasserin  |4 aut 
700 1 |a Kim, Whayoung  |e verfasserin  |4 aut 
700 1 |a Kang, Sukin  |e verfasserin  |4 aut 
700 1 |a Park, Hyeon Woo  |e verfasserin  |4 aut 
700 1 |a Yoon, Kyung Jean  |e verfasserin  |4 aut 
700 1 |a Sheen, Dong Sun  |e verfasserin  |4 aut 
700 1 |a Lee, Seho  |e verfasserin  |4 aut 
700 1 |a Hwang, Cheol Seong  |e verfasserin  |4 aut 
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773 1 8 |g volume:35  |g year:2023  |g number:43  |g day:19  |g month:10  |g pages:e2200659 
856 4 0 |u http://dx.doi.org/10.1002/adma.202200659  |3 Volltext 
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