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231223s2007 xx |||||o 00| ||eng c |
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|a 10.1109/TUFFC.2007.573
|2 doi
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|a eng
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|a Jung, Dong J
|e verfasserin
|4 aut
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| 245 |
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|a Key integration technologies for nanoscale FRAMs
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|c 2007
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|a Text
|b txt
|2 rdacontent
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|a ƒaComputermedien
|b c
|2 rdamedia
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|a ƒa Online-Ressource
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|2 rdacarrier
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|a Date Completed 14.03.2008
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|a Date Revised 15.02.2008
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|a published: Print
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|a Citation Status MEDLINE
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|a We discuss key technologies of 180-nm node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with metal-insulator-metal (MIM) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise: etching technology to have less plasma damage; stack technology for the preparation of robust ferroelectrics; capping technology to encapsulate cell capacitors; and vertical conjunction technology to connect cell capacitors to the plate line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but also to ensure a sensing margin of 300 mV in opposite-state retention, even after 1000 hour suffering at 150 degrees C
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|a Journal Article
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|a Kim, Hyun-Ho
|e verfasserin
|4 aut
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| 700 |
1 |
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|a Kim, Kinam
|e verfasserin
|4 aut
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| 773 |
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|i Enthalten in
|t IEEE transactions on ultrasonics, ferroelectrics, and frequency control
|d 1986
|g 54(2007), 12 vom: 30. Dez., Seite 2535-40
|w (DE-627)NLM098181017
|x 1525-8955
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| 773 |
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|g volume:54
|g year:2007
|g number:12
|g day:30
|g month:12
|g pages:2535-40
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|u http://dx.doi.org/10.1109/TUFFC.2007.573
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