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241019s2024 xx |||||o 00| ||eng c |
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|a 10.1109/TPAMI.2024.3483654
|2 doi
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|a pubmed25n1262.xml
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|a (DE-627)NLM379099411
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|a (NLM)39423084
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|a DE-627
|b ger
|c DE-627
|e rakwb
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|a eng
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| 100 |
1 |
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|a Wang, Zhehui
|e verfasserin
|4 aut
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|a Enabling Energy-Efficient Deployment of Large Language Models on Memristor Crossbar
|b A Synergy of Large and Small
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|c 2024
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|a Text
|b txt
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|a ƒaComputermedien
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|a ƒa Online-Ressource
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|a Date Revised 22.10.2024
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|a published: Print-Electronic
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|a Citation Status Publisher
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|a Large language models (LLMs) have garnered substantial attention due to their promising applications in diverse domains. Nevertheless, the increasing size of LLMs comes with a significant surge in the computational requirements for training and deployment. Memristor crossbars have emerged as a promising solution, which demonstrated a small footprint and remarkably high energy efficiency in computer vision (CV) models. Memristors possess higher density compared to conventional memory technologies, making them highly suitable for effectively managing the extreme model size associated with LLMs. However, deploying LLMs on memristor crossbars faces three major challenges. Firstly, the size of LLMs increases rapidly, already surpassing the capabilities of state-of-the-art memristor chips. Secondly, LLMs often incorporate multi-head attention blocks, which involve non-weight stationary multiplications that traditional memristor crossbars cannot support. Third, while memristor crossbars excel at performing linear operations, they are not capable of executing complex nonlinear operations in LLM such as softmax and layer normalization. To address these challenges, we present a novel architecture for the memristor crossbar that enables the deployment of state-of-the-art LLM on a single chip or package, eliminating the energy and time inefficiencies associated with off-chip communication. Our testing on BERT Large showed negligible accuracy loss. Compared to traditional memristor crossbars, our architecture achieves enhancements of up to 39× in area overhead and 18× in energy consumption. Compared to modern TPU/GPU systems, our architecture demonstrates at least a 68× reduction in the area-delay product and a significant 69% energy consumption reduction
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|a Journal Article
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| 700 |
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|a Luo, Tao
|e verfasserin
|4 aut
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| 700 |
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|a Liu, Cheng
|e verfasserin
|4 aut
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| 700 |
1 |
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|a Liu, Weichen
|e verfasserin
|4 aut
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| 700 |
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|a Goh, Rick Siow Mong
|e verfasserin
|4 aut
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| 700 |
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|a Wong, Weng-Fai
|e verfasserin
|4 aut
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| 773 |
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|i Enthalten in
|t IEEE transactions on pattern analysis and machine intelligence
|d 1979
|g PP(2024) vom: 18. Okt.
|w (DE-627)NLM098212257
|x 1939-3539
|7 nnas
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| 773 |
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|g volume:PP
|g year:2024
|g day:18
|g month:10
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|u http://dx.doi.org/10.1109/TPAMI.2024.3483654
|3 Volltext
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